Complex Programmable Logic Devices (CPLDs) are becoming a staple for modern digital design. Although CPLD’s have their limitations (primarily for digital and low-power architectures), they are hard to beat from a total package perspective of low power consumption, on-the-fly design flexibility, and robust operation. SECO USA engineers have used CPLD’s and FPGA’s for purposes ranging from very sophisticated (screen rotation/timing) to simple (GPIO manipulation, combinatorial logic and level shifting), but the purpose of this topic is to address their use to resolve unforeseen design issues.
One good example of this is a recent design project where we had just completed the design and test of a low-rate initial production (LRIP) board. We took the product through multiple certifications (e.g. MIL-SPEC, EMI, environmental, FCC, cellular) and were ramping up for production. Any change in the hardware would have significant impact on schedule and cost for the project, but since the board was completely tested to the requirements, the customer authorized it for production.
However, further testing at the customer’s site uncovered two unforeseen problems: The first problem dealt with ungracefully connecting and breaking power. The unit was designed to be powered from either of two hot swappable external sources, with discrete logic to prioritize and automatically select which source to use. This worked in bench testing, but when used in the field, a noisy connect or disconnect cycle could hang the unit in an indeterminate state. The second issue was that the external supplies were not voltage matched and thus, vulnerable to backfeed. This meant that the two sources could never be enabled simultaneously. Between these two problems, the unit could not be fielded as it was designed, so the customer was left with the choice of modifying the cable with a diode (increasing power use and shortening the run time in a battery powered device), modifying what the device was connected to (not possible), or modifying the PCB of unit we had designed. None of these choices were desirable, so SECO USA decided to determine if there was solution using the CPLD. This particular scenario was not foreseen in the design of the original circuitry, but since hooks were put in place to manipulate some of the power sequencing, SECO USA determined it was theoretically possible to tackle both problems with a firmware change.
The power path control was designed using dual discrete comparators to detect the sources. The comparator outputs were routed to the CPLD where simple combinatorial logic prioritized one source and CPLD outputs controlled discrete FETs to switch between the sources. In a clean connect or disconnect, this allowed uninterrupted operation throughout the hot swap. The first issue became apparent as the customer began field testing. The field connect and disconnect cycle was noisy and the simple logic controls could not always determine correctly which source was present. An easy fix for this would have been some switch overlap time, however, since the supply voltages did not match, backfeed could damage a supply or drain a battery. Adding a series diode to the source feed cable was considered, but the resulting power loss would have significantly impacted the run time of a battery. So we needed to add both debouncing and hysteresis in the CPLD to make the source switching work.
The first step to a solution was debouncing the input. This required a clock source and a determination of how many samples of the input were needed to cover the worst case connect or disconnect cycle. Additionally, the system required that the two sources could never be enabled at the same time. Another calculation was made for worst case “off” time, i.e.: How long could we run with both supplies off before the input voltage sagged below the minimum required to keep the unit running? Fortunately, the debouncing time required was shorter than the maximum “off” time. This meant that the debouncing solution was successfully implemented, however we still had an issue with priority in multiple connect and disconnect cycles.
This led to the second step, which was to prevent the possibility of an intentional disconnect during the debouncing phase. For this step, we needed to add hysteresis. By implementing hysteresis, we were able to prevent the unit from prioritizing a non-existent power source and shutting itself off. We determined that one second was long enough for the stabilization and short enough that it would not affect the end user. Back-to-back source swaps were not permitted in less than one second. This was an effective solution and allowed hot swaps as fast as was physically possible without any glitching.
The key to these solutions was the fact that the initial simple combinatorial logic for the source switching was implemented in the CPLD. This allowed us to update the firmware to incorporate a much more complex control system without the need to modify the hardware design. In fact, we were able to reprogram the CPLD without even opening the units. This implementation saved us from having to go to an expensive and time consuming PCB revision at a critical time in the project schedule.
